Although no one wants to admit that Moore’s Law is dead, it is becoming more and more difficult to improve the process technology, and TSMC is in great trouble at 3nm.
TSMC once claimed that the 3nm N3 process can increase the integration density by as much as 60-70% compared to the 5nm N5.
However, a recent paper from TSMC admits that,The area of the SRAM cell of the N3 process is 0.0199 square microns, which is only 5% smaller than the 0.021 square microns of the N5 process!
To make matters worse, the so-called second-generation 3nm process N3E has an SRAM cell area of 0.021 square microns, which is no different from the N5 process!
The transistor density in this case is only regarding 31.8 million per square millimeter.
at the same time,The SRAM unit area of the Intel 7 process (formerly 10nm ESF) is 0.0312 square microns, while the Intel 4 process (formerly 7nm) has shrunk to 0.024 square microns, an improvement of 23%, which is almost the same as TSMC’s 3nm process.
Looking at it this way, there is some reason for Intel’s process name change.
In addition, some data show that by the 2nm and later processes, the transistor density will reach regarding 60 million per square millimeter, but so-called “forksheet” transistors are required, and it will take several years to wait.
SRAM is generally used as a cache in modern chipssuch as the 81MB cache in the Ryzen 9 7950X, such as the 123MB cache in the NVIDIA AD102 core,They often require advanced process support, otherwise the area and cost will be very exaggerated.
In fact, the first step in testing a new process is generally to see whether the size and density of SRAM have been significantly improved.
It seems that the way chip manufacturers are increasingly using chiplets and various complex packaging technologies is right, and relying solely on process technology is becoming increasingly unfeasible.
