AMD’s Next-Gen EPYC Processors: The Power and Innovation of the SP7 Platform

2023-09-10 00:10:19
AMD SP7 platform can have up to 16 memory channels. According to famous leaker YuuKi_AnS, who has seen a server maker’s roadmap, AMD’s 6th generation EPYC processor, codenamed Venice, will use the all-new SP7 socket. He claims that this new platform can support up to 16 memory channels, ensuring enough memory bandwidth for CPUs with hundreds of cores. AMD’s 5th generation EPYC processors, codenamed “Turin”, will continue to use the existing SP5 socket. This is in line with AMD’s strategy of using one socket for two generations of server CPUs. However, its successor, the 6th generation EPYC processor codenamed “Venice” with Zen 6 cores, will use the all-new SP7 platform. This information is strictly unofficial, as AMD hasn’t discussed its data center platform in recent years. The new CPUs will support 12 or 16 memory channels with support for DDR5 and innovative memory modules like MR-DIMM and MCR-DIMM that feed the Zen 6 core. The number of cores supported by the processor is unknown, but it is expected to increase dramatically to 96 to 128 cores for the SP5 processor. Given the increased core count, the new SP7 socket is expected to increase the maximum power delivery of Venice processors. Socket SP5 can deliver up to 700W of peak power, which is plenty for today’s CPUs, but with AMD’s 6th generation EPYC CPUs, this number is likely to increase significantly. Given that market players like Intel and TSMC are experimenting with various innovative cooling systems for upcoming multi-chip solutions that consume and dissipate well over 1kW (1,000W). , AMD’s CPUs in 2025-2026 are expected to be at a similar level. The unknown is the number of pins on the SP7 processor. SP5 has 6,096 pins, so it’s reasonable to expect that a CPU with up to 16 memory channels and high power consumption will use quite a few pins. On the other hand, the larger CPU package will allow AMD to put more chiplets in the processor package, increasing the number of cores and features. AMD has not publicly talked about 6th generation EPYC processors, so please take the leaked information with a grain of salt. Even if it’s accurate for now, AMD may change its plans. Source: Tom’s Hardware – AMD Next-Gen EPYC Venice Zen 6 CPUs Reportedly Drop Into New SP7 Platform Commentary: I was curious about the socket change in Zen6 EPYC, so I looked into it. It seems that the reason for the socket change is that the memory channels will be updated to a maximum of 16 channels. I don’t think there will be any changes to sockets on desktops even with Zen6. I think it’s better to increase memory speed than to change sockets. The reason why we increase the number of memory channels on the server is because the server has an environment where multi-threading performance can be used to the maximum due to virtualization, and multi-threading performance is in question. The general style of commercial servers is to divide the machine power of a single server through virtualization and use it fairly according to the usage fee. You can rest assured that a single-user PC for general use will not require similar performance. Please note that the information may change in the future. I think it’s about time for information on CPUs for Zen6 clients to come out, but it’s not coming out very often. Strix Point will be available early next year (CES). I would like information on Zen6 APU and Zen6 MCM soon.
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