2023-06-13 21:20:00
Read full version
Mykola Khizhnyak
The PCI-SIG Consortium has published version 0.3 of the specifications for the upcoming PCI Express 7.0 interface standard, which will offer significantly higher bandwidth and data transfer rates compared to the current PCIe 5.0 standard. The final specifications for PCIe 7.0 are scheduled to be adopted in 2025.
Image Source: PCI-SIG
PCI Express 7.0 will offer data transfer rates of 128 GT/s per pin. In comparison, the upcoming PCIe 6.0 standard will provide data transfer rates up to 64 GT/s per pin, while the current PCIe 5.0 offers 32 GT/s. Thus, all 16 lanes of PCIe 7.0 will be able to provide an impressive throughput of 512 GB / s in duplex. PCIe 7.0 will use quad-signaled pulse amplitude modulation (PAM4), 1b/1b coding, and Forward Error Correction (FEC) to improve transmission speed and bandwidth. These features are inherited by PCIe 7.0 from the PCIe 6.0 standard.
PCI-SIG generally follows a very precise development plan for the specification, consisting of releases of several pre-release versions. Generally, version 0.3 of the specification is not specific, but here PCI-SIG notes that the main goals of this stage of development are to achieve data transfer rates of 128 GT / s, as well as the development of physical solutions that will provide reliable and energy-efficient data transfer to this speed.
As was the case with the transition from PCIe 4.0 to PCIe 5.0, the transition to PCIe 7.0 will require reducing the length of PCIe lanes to increase signal speed. In other words, this will reduce the allowable distance between the signal source (CPU) and the end point of the signal – an expansion slot for installing video cards, computing accelerators, SSDs or network adapters, unless retimers are used, which are special components that extend communication lines. The practice of using the current PCIe 5.0 interface shows that it requires the use of thicker printed circuit boards, as well as better materials for the production of various components, which in turn increases the cost of the same motherboards. How things will be with PCIe 7.0 is still unknown.
It should be clarified that the development of PCIe 7.0 is carried out primarily to meet the ever-increasing requirements for high performance computing, machine learning, networking (800GbE and above) and other corporate tasks. Although it is obvious that following some time the PCIe 7.0 standard will also appear in consumer PCs, while the developers do not say anything regarding it.
1686710994
#adoption #standard #expected