TSMC learned how to create monstrous wafer-sized two-stage processors

TSMC learned how to create monstrous wafer-sized two-stage processors

2024-04-26 18:18:00


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TSMC introduced a new generation of System-On-Wafer (CoW-SoW) platform, which uses 3D layout technology. The basis of CoW-SoW is the InFO_SoW platform, introduced by the company in 2020, which enables the creation of logic processors on the scale of an entire 300mm silicon wafer. To date, only Tesla has adapted this technology. It is used in its supercomputer Dojo.

Image source: TSMC

In the new CoW-SoW platform, TSMC will combine two packaging methods: InFO_SoW and System on Integrated Chips (SoIC). Using Chip-on-Wafer (CoW) technology, the method will place memory and/or logic directly on top of the system-on-wafer. The new CoW-SoW technology is expected to be ready for mass production by 2027.

“In the future, wafer-scale integration will allow our customers to integrate even more logic and memory components. SoW technology is no longer fiction. This is something we are already working on with our customers with the future perspective of using it in their existing products. We believe that advanced wafer-level integration technology will enable our customers to continue to increase the computing power of their AI systems or supercomputers. »said Kevin Zhang, vice president of business development at TSMC.

TSMC is now considering the possibility of combining logic processors with high-performance HBM4 memory within the CoW-SoW platform. The latter will have a 2048-bit interface and will be located directly above the logic chips. At the same time, the ability to place additional logic on a board would optimize production costs.

Wafer-scale processors (such as Cerebras’ WSE) and InFO_SoW processors deliver significant performance and efficiency benefits through high throughput, low inter-core latency, low impedance power and high energy efficiency. As an added “bonus”, these processors offer the ability to support huge amount computing cores.

However, the same InFO_SoW technology also has some limitations. For example, the efficiency of processors at a wafer scale may be limited by the efficiency of onboard memory. The CoW-SoW platform overcomes this limitation because it plans to use high-performance HBM4 memory. Additionally, InFO_SoW wafers are processed using a single process technology and do not support 3D presentation. This problem can be solved by the new CoW-SoW platform.

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